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Memory ICs
Serial interface IC for DIMMs supporting plug & play
BU9877FV
The BU9877FV is a 2-k bit EEPROM with a write protect function, developed for DIMMs (Dual In-line Memory Modules) containing a synchronous DRAM. This IC stores IDs in memory in order to enable Plug & Play functions.
*Applications144-pin DRAM modules containing syn168-pin and
chronous DRAM
*Features 1) 2-k bit EEPROM with configuration of 256 words x 8
bits. 2) Compliance with SPD data format. 3) Dual-line serial (I2C bus) interface.
4) Protective functions enabled by a one-time ROM and write protect pin. Soft ware protection. as a one-time ROM: 00 to 7Fh. Hard ware protection (WP pin): 80 to FFh. 5) Compact SSOP-B 8-pin package.
*Absolute maximum ratings (Ta = 25C)
Parameter Applied voltage Power dissipation Storage temperature Operating temperature Input voltage Symbol VCC Pd Tstg Topr -- Limits - 0.3 ~ + 7.0 300 - 65 ~ + 125 - 40 ~ + 85 - 0.3 ~ VCC + 0.3 Unit V mW C C V
1 Reduced by 3.0mW for each increase in Ta of 1C over 25C.
*Recommended operating conditions (Ta = 25C)
Parameter Power supply voltage Input voltage Symbol VCC VIN Limits 2.7 ~ 5.5 0 ~ VCC Unit V V
1
Memory ICs
BU9877FV
*Block diagram
A0 1 2048bit EEPROM Array 8 Vcc
8bit
8bit
A1
2
Address Decoder
8bit
Slave * word Address Register
Data Register
7
WP
START A2 3 Control Circuit
STOP 6 SCL
Write Protect Control Circuit
GND
4 High voltage generator Power supply voltage detector
ACK
5
SDA
*Pin descriptions
Pin No. 1, 2, 3 4 5 6 7 8 Pin name A0, A1, A2 GND SDA SCL WP VCC I/O I -- I/O I I -- Slave address setting (pin) Input / output reference voltage of 0V Slave and word address, serial data input / output Serial clock input Write protect input Connect the power supply to this. Function
Note: The SDA pin is Nch open drain output, and should be used with external pull-up resistor. The WP pin is equipped with internal pull-down resistor, so can be left open when used.
*Electrical characteristics (unless otherwise noted, Ta = - 40 to + 85C, Vcc = 2.7V to 5.5V)
Parameter Input high level voltage Input low level voltage Output low level voltage Input leakage current 1 Input leakage current 2 Output leakage current Operating current consumption Standby current SCL frequency Symbol VIH VIL VOL ILI1 ILI2 ILO ICC ISB fSCL Min. 0.7VCC -- -- -1 -1 -1 -- -- -- Typ. -- -- -- -- -- -- -- -- -- Max. -- 0.3VCC 0.4 1 20 1 3.0 2.0 100 Unit V V V A A A mA A kHz Conditions -- -- IOL = 3.0mA (SDA) VIN = 0V ~ VCC VIN = 0V ~ VCC (WP) VOUT = 0V ~ VCC VCC = 5.5V, fSCL = 100kHz VCC = 5.5V, SDA * SCL = VCC -- Measurement circuit -- -- Fig.1 Fig.2 Fig.2 Fig.2 Fig.3 Fig.4 --
2
Memory ICs
BU9877FV
*Measurement circuits
VCC VCC 3.0mA SDA VOL GND VOUT = 0 ~ VCC VIN = 0 ~ VCC ILO ILI
VCC
VCC A0, A1, A2 SDA, SCL, WP
A
GND
V
Data set when output is LOW
Fig. 1 LOW output voltage measurement circuit
Fig. 2 Input / output leakage current measurement circuit
VCC
A
VCC 100kHz clock Write / read input SCL
ICC
SDA A0, A1, A2 GND
VCC
WP
Fig. 3 Current consumption measurement circuit
VCC
VCC
A
VCC SCL
ISB
SDA
A0, A1, A2 GND
WP
Fig. 4 Standby current measurement circuit
3
Memory ICs
BU9877FV
*Circuit operation I / O timing (1) Synchronous data
tR SCL tF t HIGH
t HD: STA
t SU: DAT
t LOW
t HD: DAT
SDA (input)
t BUF t PD t DH
SDA (output)
SCL t SU: STA SDA t HD: STA t SU: STO
START BIT
STOP BIT
Fig. 5
* Reading of input is done at the rising edge of SCL. * Output of data is synchronized to the falling edge of SCL.
4
Memory ICs
BU9877FV
*Operation timing characteristics (unless otherwise noted, Ta = - 40 to + 85C , Vcc = 2.7V to 5.5V)
Parameter Data clock HIGH time Data clock LOW time SDA / SCL rise time SDA / SCL fall time Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus release time prior to start of transfer
1
Symbol t HIGH t LOW tR tF t HD: STA t SU: STA t HD: DAT t SU: DAT t PD t DH t SU:STO t BUF t WR1 t WR2 tI
Min. 4.0 4.7 -- -- 4.0 4.7 0 250 -- 0.3 4.7 4.7 -- -- --
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- -- 1.0 0.3 -- -- -- -- 3.5 -- -- -- 10 15 0.1
Unit s s s s s s ns ns s s s s ms ms s
Internal write cycle time
2
Effective noise elimination interval (SCL, SDA pins)
1 VCC = 4.5V to 5.5V 2 VCC = 2.7V to 5.5V
(3) Start condition (start bit recognition) Before executing the various commands, a start condition (start bit) must be input. This is recognized when SCL is HIGH and SDA falls from HIGH to LOW. If a start condition is not input, no commands will be received. (4) Stop condition (stop bit recognition) To terminate the various commands, a stop condition (stop bit) must be input. This is recognized when SCL is HIGH and SDA rises from LOW to HIGH. (5) Precautions concerning the write command With the write command, internal writing is initiated by inputting the stop bit after the data has been input. (6) Device addressing (specifying the slave address) The master address should be output first, followed by the start condition, and then the slave address. The first four bits of the slave address are used to recognize the device type. The device code for this IC is fixed at "1010". When accessing the write protect register, a device code of "0110" is used. The next three bits of the slave address (A2, A1, A0) are used to select the device, and the IC begins to function only if the data input for A2 to A0 matches the states of input pins A2 to A0. Consequently, up to eight of these ICs may be connected on the same bus, depending on the combination of A2 to A0. The last bit of the slave address (R / W) is used to specify either writing or reading, and is as shown below. R / W set to 0: Writing or Random Read R / W set to 1: Reading
Device type 1010 0110
Device address A2 A2 A1 A1 A0 A0 R/W W Access to memory Access to write protect register
5
Memory ICs
(7) Write protect command The write protect command is used to prohibit writing of data to addresses 00 to 7Fh, among the 256 word address data. Be aware that once a write protect register has been specified, it cannot be canceled (one-time memory). The write protect command can function regardless of the state of the WP pin. (8) WP (write protect pin) Setting the WP pin to Vcc (HIGH level) has the same effect as using the write protect command, and inhibits writing of data to addresses 80 to FFh, among the 256 word address data. Normal writing is enabled by setting this pin to GND (LOW level). (If the write protect command is used to inhibit writing, data cannot be written regardless of the status of the WP pin.) The WP pin is equipped with an internal pull-down resistor, so if the protect function is not being used, this should be left open or set to GND.
BU9877FV
(9) ACK signal The acknowledge signal (ACK signal) is determined by the software, and indicates whether or not the data has been correctly transmitted. Regardless of whether the address is a master or slave address, the device on the transmitter (sending signal) side (the master when a slave address is input for a write command or a read command, and the EEPROM when read command data is output) opens the bus after this 8-bit data is output. With a device on the receiving (reception) side (the EEPROM when a slave address is input for a read command or write command, and the master when data is output for a read command), SDA is set to LOW during the nine-clock cycle, and the acknowledge signal (ACK signal) is output when 8-bit data is received. For writing operations, the acknowledge signal (ACK signal) is output in the LOW state each time that 8-bit data (word address or write data) is received. In reading operations, 8-bit data (read data) is output, and then the acknowledge signal (ACK signal) in the LOW state is detected. If the acknowledge signal (ACK signal) is detected and no stop condition is sent from the master (microcomputer) side, this IC continues to output data. If the acknowledge signal (ACK signal) is not detected, this IC interrupts the transmission of data, recognizes a stop condition (stop bit), and terminates the reading operation. The IC then enters the standby mode.
Start condition SCL (from master)
t PD
1
8
9
SDA (master output data)
SDA (data output from the BU9877FV)
Acknowledge signal (ACK signal)
Fig. 6 Acknowledge signal (ACK signal) response (when slave address is input for writing or reading)
6
Memory ICs
(10) Timing charts
Start condition 1 SCL 8 9 17 18 26 27
BU9877FV
Stop condition
SDA
1
0
1
0
A2
A1
A0
0
WA7 WA6
WA0
D7
D0
Slave address
Word address
Write data ACK signal (output)
Fig. 7 Byte write cycle
* Data is written to the address specified by the word address (n address). * After 8 bits of data are input, a stop bit is generated. This initiates writing of the data to the memory cell.
Start condition 1 SCL 8 9 18 Stop condition
SDA
1
0
1
0
A2
A1
A0
1
D7
D6
D5
D2
D1
D0
1
Slave address ACK signal (output)
Read data ACK signal (input)
Fig. 8 Current read cycle
* This IC has an internal circuit address counter to store the previously accessed address in the memory. If the previous command was a write command, the write word address data (n) is read, and if the previous command was a read command, the read word address data (n) incremented by one address (n + 1) is read. * If the ACK signal LOW following D0 is detected and no stop condition is sent from the master side, reading can be continued sequentially to the next data.
7
Memory ICs
BU9877FV
Start condition
Start condition
Stop condition
SCL
SDA
1
0
1
0
A2
A1 A0 0
WA7
WA0
1
0
1
0
A2
A1
A0
1
D7
D0
1
Slave address
Word address
Slave address ACK signal (output)
Read data ACK signal (input)
Fig. 9 Random read cycle
* This command enables reading of the data at the specified word address. * If the ACK signal LOW following D0 is detected and no stop condition is sent from the master side, reading can be continued sequentially to the data of the next word address. * To terminate this command, HIGH is input at the ACK signal timing (following any D0), then stop condition is input.
Start condition
Stop condition
SCL
SDA
1
0
1
0
A2
A1
A0
1
D7
D0
D7
D0
Slave address
Read data ACK signal (output)
Read data n+a ACK signal (input)
Fig. 10 Sequential read cycle
* If the ACK signal is detected following D0 and no stop condition is sent from the master side, reading can be continued sequentially to the data of the next word address. * To terminate this command, HIGH is input at the ACK signal timing (following any D0), then stop condition is input.
8
Memory ICs
BU9877FV
Start condition 1 SCL 8 9 17 18 26 27
Stop condition
SDA
0
1
1
0
A2
A1
A0
0
DON'T CARE
DON'T CARE
Slave address
Word address
Write data
ACK signal (output)
Fig. 11 Write protect cycle
* The write protect command is used to prohibit writing of data to addresses 00 to 7Fh, among the 256 word address data, and cannot be altered (one-time memory). * The command is canceled if a stop condition has been input before the 27th clocks. * If the write protect command is input when the protect status is already in effect, the command is canceled.
*External dimensions (Units: mm)
3.0 0.2 8 6.4 0.3 4.4 0.2 5
1.15 0.1
1 0.1
4
(0.52)
0.65 0.22 0.1
0.3Min. 0.1
SSOP-B8
0.15 0.1
9

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